The present invention relates to a semiconductor device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor on a single substrate, and a method of producing the same.
A semiconductor device having a BiCMOS structure, i.e., having a bipolar transistor and a CMOS transistor on a single substrate is conventional. However, a conventional method of producing such a semiconductor device is that an n-type collector region is not achievable without resorting to extra steps, i.e., a lithographic step, an ion implanting step and a diffusing step which increase the production cost of the device. In addition, to guarantee a sufficient breakdown voltage between a base and a collector, a base diffusion layer and a collector diffusion layer must be spaced by a great distance, hindering the miniaturization of the transistor.
Japanese Patent Laid-Open Publication No. 7-142498 teaches a method capable of producing the above semiconductor device with a reduced number of production steps. This method, however, brings about another drawback that the polysilicon layer of an emitter electrode and a gate electrode must be overetched by 150% to 300%. Such an amount of overetching causes a CMOS gate electrode to have an inversely tapered configuration and thereby brings a source-drain diffusion layer out of alignment with the ends of the gate electrode. As a result, the current drive ability of the transistor is deteriorated. Moreover, when a direct contact for leading out an electrode from a diffusion layer region existing in a memory cell is present, a connection resistance between the diffusion layer and the direct contact lead-out electrode is increased by about several ten to several hundred kilohms, rendering the operation of the memory cell unstable.
Technologies relating to the present invention are also taught in, e.g., U.S. Pat. No. 5,358,882 to Bertagnolli et al.